DK-DEV-5SGXEA7N【PDF 109/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

Guidelines

4-39

A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high,

and being held high for at least three inclk cycles.

You must bring the clkswitch signal back low again to perform another switchover event. If you do not

require another switchover event, you can leave the clkswitch signal in a logic high state after the initial

switch.

Pulsing the clkswitch signal high for at least three inclk cycles performs another switchover event.

If inclk0 and inclk1 are different frequencies and are always running, the clkswitch signal minimum high

time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.

Figure 4-38: Manual Clock Switchover Circuitry in Stratix V PLLs

clkswitch

Clock Switch

Control Logic

inclk0

inclk1

muxout

N Counter

refclk

PFD

fbclk

You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL

megafunction. When you specify the switchover delay, the clkswitch signal must be held high for at least

three inclk cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.

Related Information

Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide

Provides more information about PLL software support in the Quartus II software.

Guidelines

When implementing clock switchover in Stratix V PLLs, use the following guidelines:

? Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each

other. Failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function

properly.

? When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100%

(2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause the PLL

to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the

input and output clocks.

? Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual

clock switchover event. Failing to meet this requirement causes the clock switchover to not function

properly.

? Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth

PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a high-

bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock

to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL

also increases lock time.

? After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new

clock. The time it takes for the PLL to relock depends on the PLL configuration.

? The phase relationship between the input clock to the PLL and the output clock from the PLL is important

in your design. Assert areset for at least 10 ns after performing a clock switchover. Wait for the locked

signal to go high and be stable before re-enabling the output clocks from the PLL.

Clock Networks and PLLs in Stratix V Devices

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